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Apollo Core Rope Memory (Apollo Guidance Computer Part 30)

CuriousMarc・2 minutes read

A genuine Apollo Guidance Computer was restored, guiding Apollo missions to the Moon, using core rope memory for program storage. Through various modules and testing, issues with core rope memory were addressed and resolved, leading to successful recovery and preservation of historic AGC software.

Insights

  • AGC, the computer guiding Apollo missions to the Moon, was restored by a team led by Mike Stewart, who recovered software from various sources and developed innovative tools like a portable core rope reader.
  • The intricate workings of core rope memory, with its unique core flipping scheme involving set wires, inhibit wires, and parity wires, were meticulously explained and demonstrated, highlighting the complexity and precision required to read and manipulate data stored in this early form of memory technology.

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Recent questions

  • What is the Apollo Guidance Computer?

    A computer that guided Apollo missions to the Moon.

  • How was the AGC software recovered?

    Through preservation efforts and innovative technology.

  • What is core rope memory?

    A dense, read-only memory used in AGC.

  • What challenges were faced during AGC testing?

    Issues with missing blocks and reading sections.

  • How did the team resolve software recovery issues?

    By rectifying errors and reintroducing faulty logic.

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Summary

00:00

"Restoring Apollo Guidance Computer: A Journey"

  • Restored a genuine Apollo Guidance Computer in 24 episodes
  • AGC guided Apollo command module and LM to the Moon
  • First computer with integrated circuits and fly by wire
  • Real-time software could recover instantly from a crash
  • Recovered Apollo 11 LM software from Draper Labs collection
  • Don Eyles preserved some AGC listings
  • AGC used core rope memory for program storage
  • Core rope memory was read-only and denser than traditional memory
  • Recovered AGC software from Computer History Museum's AGC
  • Mike Stewart developed a portable core rope reader for AGC software recovery

14:11

"AGC Modules Acquisition and Testing Challenges"

  • Mike obtained Retread 50 from the Computer History Museum and Sundial E from the MIT Museum.
  • Seven different modules of various versions of Sundance for Apollo 9 were acquired from Don Eyles and Eldon Hall.
  • The AGC modules that were sold were included in the seven figures obtained.
  • Apollo 11 is complete, but Apollo 12 is missing the Command Module ropes.
  • Mike's contraption, designed for testing with actual ropes, has been completed but not yet tested.
  • A rope jumper from the real AGC was installed for a full power test, reading all zeros correctly.
  • Module B4 from Luminary 69, flown on Apollo 10, was acquired from a generous collector.
  • The contraption takes in 14 volts to match the AGC, with a hot swap controller for protection.
  • Issues arose during testing, with blocks missing and problems reading certain sections.
  • Core rope memory is explained, detailing the data wires, sense amplifiers, and addressing scheme.

28:49

"Core Rope Memory: Flipping Cores and Parity"

  • The core rope test involves wired cores that can be flipped back and forth using three wires.
  • The oscilloscope displays the core flipping process with set wire, reset wire, and sense signals.
  • Flipping the core is demonstrated by activating the set wire, causing the core to change state.
  • Flipping the core back and forth is shown to be affected by the material's magnetic properties.
  • Core rope memory utilizes a unique core flipping scheme involving set wires, inhibit wires, and anti wires.
  • The process involves pulsing the set wire to flip all cores to a specific state and using inhibit wires to select individual cores.
  • The addition of inhibit wires in specific patterns allows for the selection of single cores within the array.
  • The introduction of parity wires aims to reduce inhibit current and correct half-inhibited cores.
  • The parity inhibit wires are used to address cores with opposite address parity, preventing half-inhibited states.
  • A design error in the use of parity wires leads to unintended consequences, causing cores to be partially flipped and affecting data accuracy.

43:09

Address Selection Cycle in Core Rope Module

  • To inhibit current to the whole plane and patch away the issue, a correct address selection cycle in a Block II core rope module is demonstrated, requiring the use of inhibits, anti wires, parity wires, resets, and set lines.
  • The simulation can automatically select a core address in octal, with the ability to simulate the entire cycle of selection, flipping the core, and resetting the array to read the selected core.
  • Mike identifies a problem with the parity inhibit wire calculation, rectifying it by recompiling the FPGA code and reintroducing the faulty logic to successfully read the ropes.
  • After fixing the issue, the rope is restarted, and the correct reading of addresses is confirmed, leading to the identification of module B4 from Luminary 69, showcasing the successful resolution of the problem.
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